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Si2704/05/06/07-A10
EMI M ITIGATING 2.1 X 5 W CLASS D A UDIO AMPLIFIER
Features

Digital input Delta-Sigma PWM Patent-pending EMI mitigation AM radio band noise-free notch GSM/iPhone friendly Wideband PWM carrier spreading Power stage slew rate control Power stage feedback for PSR/THD 2x 5 W @ 3 BTL; 2x 3 W @ 8 BTL 88% efficiency with >50 dB PSRR 95 dB dynamic range and <0.1% THD Stereo PWM DAC line analog outputs Master/slave I2S w/ 3 inputs & 1 output Automatic digital audio rate detection Standard audio rates from 32-192 kHz Audio activity detector w/ auto-standby Operates from external XTAL or clock Buffered master/regulator clock output

Programmable 7 band parametric EQ, dynamic range compressor, tone control Crossbar input mixer with scaling Digital tone and alert generation 128 dB volume control in 0.5 dB steps Multiple low power operating modes Over-current and over-temperature detection w/ auto recovery Pop and click free operation Standard 2-wire control w/ 2 addresses System flexibility w/ 3 multi-function pins Dual supply voltage: 2.7-3.6 V main and 4.0-6.6 V power stage Available in 4x4 24-pin Power QFN and 7x7 48-pin Power eTQFP package Both Pb-free/RoHS compliant
Ordering Information: See page 37.
Pin Assignments
Applications

Si2704/05/06/07
XTLO
PMP/MP3 docking stations Portable consumer audio electronics Table top and portable radios

Active/wireless speakers TVs and monitors TV sound bars
24 DCLK DIN VIO SCLK SDIO CLKO 1 2 3 4 5 6 7 MFP3
23
22
21
20
19 18 17 OUTPL OUTNL GNDL GNDR OUTNR OUTPR
Description
The Si2704/05/06/07 EMI mitigating 2.1 digital audio processing Class D amplifier integrates a power stage, PWM DAC, and digital audio processing (DAP) for simplified, low cost, power efficient system designs in consumer audio electronics. The digital input amplifier features delta-sigma PWM and innovative EMI mitigation technology for producing high-quality audio while effectively managing PWM switching noise for enhanced EMI compliance and AM/FM radio co-existence, while also being GSM/iPhone friendly.
VPPL 16 15 14 13 12 VPPR
39
VDD
XTLI
GND PAD (Back Paddle)
Top Down View 24-Pin QFN Package 8 AUXOL 9 AUXOR 10 MFP1 XTLO XTLI 11 OUTSEL/MFP2 RSTB
GND
VDD
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
NC
38
NC
37 36 35 34 33 32 31
Si270x Digital Class-D Amplifier
2.7 - 3.6 V Supply
VDD
NC DFS DCLK
NC
Functional Block Diagram
1 2 3 4 5 6 7 8 9 10 11 12
RST
DFS
NC VPPL OUTPL GND OUTNL GNDL GNDR OUTNR GND OUTPR VPPR NC
LDO Power
DIN VIO
CLKO
Clock Generation DSP
CH 1
LF
GND SCLK
PWM
Stage
GND PAD (Back Paddle)
30 29 28 27
SDIO CLKO NC
I2S
1.62 - 3.6 V Supply
MFP 2-Wire Control
VIO
I S/AAD Mixer ASRC Tone Gen. Cross-over Filter Volume Control Tone Control 7-Band EQ DRC
2
Feedback
VPP
4.0 - 6.6 V Supply
NC NC
Top Down View 48-Pin eTQFP Package
13 14 15 16 17 18 19 20 21 22 23 24
26 25
GND
NC
VOL/MFP1
NC
NC
OUTSEL/MFP2
SLEEP/MFP3
AUXOL
AUXOR
NC
NC
Power PWM
CH 2 RF
Stage
Over Current Over Temp
MFP Control System Control PWM DAC
AUXOL/R
Rev. 0.6 8/10
Copyright (c) 2010 by Silicon Laboratories
Si2704/05/06/07-A10
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
NC
Si2704/05/06/07-A10
2
Rev. 0.6
Si2704/05/06/07-A10 TABLE O F CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. Typical System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1. PWM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1. PWM Switching Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.2. EMI Mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1. Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2. Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3. Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4. Power Down Mode and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 20 20
4.3. Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1. Multi-Function Pins (MFPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.2. Output Mode Configuration (Si2705/07 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4.1. Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.2. Reference Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5. Digital Audio I2S Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.5.1. Auto-Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2. Audio Activity Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3. Digital Audio Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.4. Audio data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.5. I2S Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1. Parametric Equalization (Si2706/07 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2. Tone Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3. De-Emphasis (Si2706/07 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.4. Crossover Filter (Si2706/07 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.5. Digital Volume Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.6. Dynamic Range Compression (Si2706/07 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.7. Hard Signal Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.8. DC Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.9. Tone and Alert Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 24 24 27 27 28 28 28 29 30 30 30
4.6. Digital Audio Processing (DAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.7. Fault Detection and Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8. Power Supply and Grounding Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.10. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1. 24-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2. 48-Pin eTQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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8.1. 24-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2. 48-Pin eTQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1. Si2707 Top Mark (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.3. Si2707 Top Mark (eTQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.4. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
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1. Electrical Specifications
Table 1. Recommended Operating Conditions1
Parameter Power Output Supply Voltage Main Supply Voltage Interface (I/O) Supply Voltage Load Impedance Ambient Temperature Junction Temperature Case Delta from Junction Delta from Junction to Ambient3 Symbol VPP VDD VIO RL TA TJ JC JA Temperature delta between junction and top center of package QFN package eTQFP Test Condition Min 4.02 2.7 1.62 -- -20 -- -- -- -- Typ -- 3.3 -- 3-8 25 -- -- 25 30 Max 6.6 3.6 3.6 -- 85 135 5 -- -- Unit V V V C C C/W C/W C/W
Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless otherwise stated. 2. Operation with VPP as low as 3 V is possible at reduced performance. 3. The JA is layout-dependent; therefore, PCB layout must provide adequate heat-sink capability. The.JA is specified, assuming adequate ground plane as in "AN470: 270x Layout Guidelines."
Table 2. Absolute Maximum Ratings1
Parameter Power Output Supply Voltage Main Supply Voltage Interface (I/O) Supply Voltage Input Current2 Input Voltage2 Operating Temperature Junction Temperature Storage Temperature Symbol VPP VDD VIO IIN VIN TA TJ TA Value -0.5 to 7.0 -0.5 to 3.9 -0.5 to 3.9 10 -0.3 to (VIO + 0.3) -20 to +85 150 -55 to +150 Unit V V V mA V C C C
Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. For input pins SCLK, SDIO, DCLK, DFS, DIN, RST, OUTSEL, MFPx.
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Table 3. DC Characteristics--Supplies and Interfaces
(VDD = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, VPP = 4 to 6.6 V, TA = -20 to +85 C)
Parameter Start Up Time
Symbol TONSB
Test Condition From Standby Mode with CLKO enabled From Standby Mode with CLKO disabled
Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typ -- -- -- -- 50 45 54 1.3 0.1 8 4 2 0.1 2 1.5 0.1 2 0.3
Max 2 20 20 200 -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit ms ms ms ms mA mA mA mA mA mA mA mA mA mA mA mA mA mA
TON_SLP TON_PD Active Mode Quiescent Supply Current IPQ
From Sleep Mode From Power Down Mode From VPP, No load, Both Channels Active, Spread Mode PWM From VPP, No load, Both Channels Active, Normal Mode PWM
IDQ IIOQ Standby Mode Supply Current IPSTB IDSTB
From VDD From VIO, I S Slave Mode, CLKO Disabled Standby Mode Standby Mode with CLKO enabled Standby Mode with CLKO disabled
2
IIOSTB Sleep Mode Supply Current IPSLP IDSLP IIOSLP Power Down Mode Supply Current IPPD IDPD IIOPD
Standby Mode SLEEP asserted SLEEP asserted SLEEP asserted
Input pins SCLK, SDIO, DCLK, DFS, DIN, RST, OUTSEL, MFPx High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Output pins MFPx, CLKO* High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current VOH VOL IOH IOL IOUT = 500 A IOUT = -500 A 0.8 x VIO 0.2 x VIO 0.8 x VIO -- -- -- -- -- 6 6 -- 0.2 x VIO -- -- V V mA mA VIH VIL IIH IIL VIN = VIO = 3.6 V VIN = 0 V, VIO = 3.6 V 0.7 x VIO -- -10 -10 -- -- -- -- -- 0.3 x VIO 10 10 V V A A
*Note: Valid for the configuration where MFPx is configured as an output or general purpose output.
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Table 4. DC Characteristics--Class D Amplifier
(VDD = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, VPP = 4 to 6.6 V, TA = -20 to +85 C)
Parameter Output Voltage Offset Total Drain-Source On-State Resistance (Total Bridge)*
Symbol VOS RDSON
Test Condition Differential Output VPP = 6.6 V, IO= 1A
Min -- --
Typ 10 648
Max -- --
Unit mV m
*Note: Excludes package bond wire resistance.
Table 5. AC Characteristics--Class D Amplifier
(VDD = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, VPP = 6.6 V, RL = 8 , VOL = 0 dBFS, TA = -20 to +85 C, unless otherwise noted.)
Parameter Continuous Output Power
1
Symbol PO
Test Condition THD+N = 10%, f = 1 kHz, RL = 8 THD+N = 1%, f= 1 kHz, RL = 8 THD+N = 10%, f = 1 kHz, RL = 4 THD+N = 1%, f= 1 kHz, RL = 4 THD+N = 10%, f = 1 kHz, RL = 3
Min -- -- -- -- -- -- -- -- -- -- -- --
Typ 2.7 1.9 4.7 3.4 5.0 0.1 95 92 90 87 24 35
Max -- -- -- -- -- -- -- -- -- -- -- --
Unit W W W W W % dB dB dB dB dB dB
Total Harmonic Distortion + Noise Signal to Noise Ratio/Dynamic Range
THD+N SNR
PO=1 W, f = 1 kHz Normal mode PWM, f = 1 kHz, A-weighted Normal mode PWM, f = 1 kHz, Unweighted Spread mode PWM, f = 1 kHz, A-weighted Spread mode PWM, f = 1 kHz, Unweighted
Spread Mode Common Mode PWM Carrier Peak Attenuation2 Common Mode AM Band Noise Notch Attenuation3
f = 1 kHz, Relative to Normal Mode f = 1 kHz, Measured in 10 kHz band around selected frequency
Notes: 1. Measured at filter output. Power measured at the chip output is greater. 2. Guaranteed by characterization.
3. Measured relative to the integrated noise floor in Spread mode. Guaranteed by characterization.
4. Does not include filter efficiency losses.
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Table 5. AC Characteristics--Class D Amplifier (Continued)
(VDD = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, VPP = 6.6 V, RL = 8 , VOL = 0 dBFS, TA = -20 to +85 C, unless otherwise noted.)
Power Supply Rejection Ratio
PSRR
PO = -3 dBFS, f = 1 kHz; 200 mVPP, fr = 400 Hz supply ripple f = 1 kHz f = 1 kHz, half rate PWM and 10 ns slew rate Half Rate PWM Full Rate PWM
--
50
--
dB
Crosstalk Efficiency
4
-- -- -- --
-92 88 480 960
-- -- -- --
dB % kHz kHz
PRF
Output Pulse Repetition Frequency
Notes: 1. Measured at filter output. Power measured at the chip output is greater. 2. Guaranteed by characterization.
3. Measured relative to the integrated noise floor in Spread mode. Guaranteed by characterization.
4. Does not include filter efficiency losses.
Table 6. AC Characteristics--PWM Digital to Analog Converter
(VDD = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, VOL = 0 dBFS, TA = -20 to +85 C, unless otherwise noted).
Parameter Total Harmonic Distortion + Noise Signal to Noise Ratio/Dynamic Range
Symbol THD+N SNR
Test Condition f = 1 kHz f = 1 kHz, A-weighted f = 1 kHz, Unweighted
Min -- -- -- -- --
Typ 0.02 88 85 1 0.8 -- --
Max -- -- -- -- -- 50 1
Unit % dB dB VP-P V k F
Output Voltage Swing Output Voltage Common Mode Bias Output Load-- Resistance Output Load-- Capacitance
Vout Voutcm Rload Cload AC coupled AC coupling capacitor
5 0.1
Table 7. I2S Digital Audio Interface Characteristics
(VIO = 1.62 to 3.6 V, TA = -20 to +85 C, unless otherwise noted).
Parameter DCLK Input Cycle Time DCLK Input Pulse Width High DCLK Input Pulse Width Low DFS Setup Time to DCLK DFS Hold Time after DCLK DOUT Output Delay Capacitive Loading
Symbol tCYC:DCLK tHI:DCLK tLO:DCLK tSU:DCLK tHD:DCLK TPD:DCLK CB
Test Condition
Min 70 0.4 x tCYC:DCLK 0.4 x tCYC:DCLK 10 5 0 --
Typ -- -- -- -- -- -- --
Max -- 0.6 x tCYC:DCLK 0.6 x tCYC:DCLK -- -- 35 15
Unit ns ns ns ns ns ns pF
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Figure 1. Digital Audio Timing Parameters Table 8. 2-Wire Control Interface Characteristics
(VIO = 1.62 to 3.6 V, TA = -20 to +85 C, unless otherwise noted).
Parameter SCLK Frequency SCLK Low Time SCLK High Time SCLK Input from SDIO Setup (START) SCLK Input to SDIO Hold (START) SDIO Input to SCLK Setup SDIO Input to SCLK Hold SDIO output delay SCLK input to SDIO Setup (STOP) STOP to START Time SDIO Output Fall Time SDIO Input, SCLK Rise/Fall Time Capacitive Loading Pulse Width Rejected by Input Filter
Symbol fSCL tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT TPD:DAT tSU:STO tBUF tf:OUT tf:IN tr:IN Cb tSP
Test Condition
Min 0 1.3 0.6 0.6 0.6 100 0 300 0.6 1.3 -- -- -- --
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max 400 -- -- -- -- -- 900 900 -- -- 250 300 50 50
Unit kHz s s s s ns ns ns s s ns ns pF ns
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Table 9. 2-Wire Control Interface Address Selection
CLKO Startup Voltage (Pin Connection) GND VIO (Default) 2-Wire Device Address 1001010 (0x94) 0011011 (0x36)
Table 10. Reset Timing Characteristics
(VIO = 1.62 to 3.6 V, TA = -20 to +85 C, unless otherwise noted).
Parameter CLKO Setup Time to RST CLKO Hold Time after RST
Symbol tSRST THRST
Test Condition
Min 100 30
Typ -- --
Max -- --
Unit s ns
tH R S T 70%
tSR ST
RST
30%
70%
C LK O
30%
Figure 2. Reset Timing Parameters for Configuration Mode Select
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tSU:STA tHD:STA tLOW tHIGH tr:IN tf:IN tSP tSU:STO tBUF
SCLK
70% 30%
SDIO
70% 30%
START
tr:IN
tHD:DAT tSU:DAT
tPD:DAT
tf:IN, tf:OUT
STOP
START
Figure 3. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
SDIO (Write)
START
A6-A0, 0
Command 7-0
ACK DATA ACK
Arg1 7-0
DATA ACK STOP
ADDRESS + R/W
SDIO (Read)
START
A6-A0, 1
Status 7-0
ACK DATA ACK
Response 7-0
DATA ACK STOP
ADDRESS + R/W
Figure 4. 2-Wire Control Interface Read and Write Timing Diagram
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Table 11. Reference Clock and Crystal Characteristics
(VDD = 2.7 to 3.6 V, VIO = 1.62 to 3.6 V, TA = -20 to +85 C, unless otherwise noted).
Parameter Reference Clock, Pin XTLI Supported Frequencies1 Frequency Tolerance Jitter Tolerance2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Crystal oscillator, Pins XTLI, XTLO Crystal Oscillator Frequency3 Crystal Frequency Tolerance Internal Crystal Load Capacitance Crystal Motion Resistance Reference Clock Output, Pin CLKO Frequency Range4 Load Capacitance
Symbol
Test Condition
Min
Typ
Max
Unit
2 -1000 Integrated from 20 Hz to 1 MHz VIH VIL IIH IIL VIN = VI0 = 3.6 V VIN = 0 V VI0 = 3.6 V -- 0.7xVI0 -- -10 -10
-- -- -- -- -- -- --
49 1000 50 -- 0.3xVI0 10 10
MHz ppm psrms V V A A
12.288 -1000 4 for 24.576 MHz Crystal --
-- -- -- --
24.576 1000 20 100
MHz ppm pF
120 --
-- --
24576 10
kHz pF
Notes: 1. Supported reference clock frequencies at XTLI include 2.048, 2.822, 3.072, 4.096, 4.234, 4.608, 5.645, 6.144, 8.192, 8.467, 9.216, 11.290, 11.2896, 12, 12.288, 16.368, 16.934, 18.432, 22.579, 24.576, 32.768, 32.869, 36.864, 45.158, and 49.152 MHz. 2. Required to achieve specified performance. 3. Supported crystal frequencies at XTLI include 12.288, 18.432, and 24.576 MHz. 4. 120 kHz, 240 kHz, 480 kHz, 960 kHz, 1.92 MHz, 4.096 MHz, 6.144 MHz, 8.192 MHz, 12.288 MHz, 16.384 MHz, and 24.576 MHz are available at CLKO.
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2. Typical Application Schematic
VDD 2.7 to 3.6 V C9 0.1 uF C7 0.1 uF VIO 1.62 to 3.6 V Optional L1 23 12 19 3 C1 C15 18 17 C16
RSTB DFS DCLK DIN SCLK SDIO CLKO
VPP 4.0 to 6.6 V C11 220 uF
C10 0.1 uF
C8 0.1 uF
R
VP P
VP PL
R1 C5 R2 C2
21 X1 22
XTLI XTLO
OUTPL OUTNL
20 24 1 2 4
OUTPR
U1 Si2705/07
GNDL GNDR
16 15
L2
13 14
5 6
OUTSEL AUXOR AUXOL OUTNR
L3 C3 C17 R3 C6 C18 R4 C4 L4
11
SLEEP/MFP3 AUXOL
25 C12 C13
7
8
9
Figure 5. Typical Application Schematic Table 12. Typical Application Schematic Bill of Materials
Component C1, C2, C3, C4 C15, C16, C17, C18 C5, C6 L1, L2, L3, L4 Inductor Filter 0.68 F, ceramic 0.33 F, ceramic 0.47 F, Film 10 H, 1.5 A, inductor Ferrite Bead Filter 1000 pF, ceramic 1000 pF, ceramic 100 pF, ceramic TDK MPZ2012S601A, ferrite bead
Note: When using the ferrite bead output filter with AM radio, shielded cable is recommended.
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3. Typical System Configurations
2.7-3.6 V Supply
VDD/VIO
VPP
4.0-6.6 V Supply
LF
XTLI XTLO OUTPL OUTNL
Dock
Dock I/F
CLKO
Line In
Stereo ADC
IS
2
Si270x Digital Audio Amplifier
OUTPR OUTNR
RF
User I/F
System MCU
2-Wire MFP
OUTSEL AUXOL AUXOR
HPDET
Figure 6. Basic PMP Dock System Configuration
2.7-3.6 V Supply
VDD/VIO
XTLI XTLO CLKO OUTPL
VPP
4.0-6.6 V Supply Filter
LF
Digital Media Controller
Dock
I2S DI2 I2S DO
OUTNL
Dock I/F
Radio Tuner Si473x-D Stereo ADC
I2S DIN
Si270x Digital Audio Amplifier
OUTPR
Filter
OUTNR
RF
Line In
User I/F
System MCU
2-Wire MFP
AUXOL AUXOR
HPDET
Figure 7. PMP Dock with Radio and Digital Media Controller System Configuration
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External Subwoofer
XTLI AUXOL
Digital Media Controler
IS
2
XTLO
Midrange Amplifier Si270x
L
L Midrange
R
I2C adress 0x36
R Midrange
System MCU
2-Wire
OUTSEL CLKO XTLI
Tweeter Amplifier Si270x Radio
I2S
I2C adress 0x94
L
L Tweeter
R
R Tweeter
HPDET
OUTSEL AUXOL AUXOR
Headphone
Figure 8. Stereo 2-Way Speaker System Configuration
External Subwoofer
XTLI XTLO Analog Audio 1
AUXOL
Si270x Digital Audio Amplifier
1 2
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
CLKO XTLI
Analog Audio 2
Digital Audio
Receiver & Mux Audio Processor
XTLI
Si270x Digital Audio Amplifier
1 2
DVI/PC Audio
Delay Control
Si270x Digital Audio Amplifier
XTLI
1 2
From PMP dock
Si270x Digital Audio Amplifier
1 2
Figure 9. TV Sound Bar System Configuration
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4. Functional Description
Si270x Digital Class-D Amplifier
2.7 - 3.6 V Supply
VDD
LDO Power
CLKO
Clock Generation DSP
CH 1
LF
PWM
Stage
I2S
1.62 - 3.6 V Supply
MFP 2-Wire Control
VIO
I2S/AAD Mixer ASRC Tone Gen. Cross-over Filter Volume Control Tone Control 7-Band EQ DRC
Feedback
VPP
4.0 - 6.6 V Supply
Power PWM
CH 2 RF
Stage
Over Current Over Temp
MFP Control System Control PWM DAC
AUXOL/R
Figure 10. Functional Block Diagram
The Si2704/05/06/07 EMI mitigating 2.1 x 5 W Class D audio amplifier integrates a stereo power stage, PWM DAC, and digital signal processor (DSP) to enable simplified, low cost, power efficient system designs in consumer audio electronics. The digital input amplifier features delta-sigma PWM for high quality audio while innovative EMI mitigation technology manages PWM switching noise to suppress peak emissions more than 20 dB while providing co-existence with AM/FM radio tuners. The power stage is capable of driving two 3 bridge-tied speakers with 5 W per channel at 10% THD+N from 6.6 V power supplies. It can also drive 8 bridge-tied speakers at 3 W per channel with 88% efficiency. The power stage feedback systems improve power supply rejection and harmonic distortion performance. The Si270x connects up to three synchronous I2S digital sources as either master or slave, two of which can be configured as input or output. The I2S input is converted to a common sample rate for digital audio processing using an asynchronous sample rate converter (ASRC) and a digital crossbar mixer linearly combines any of the six inputs into the three audio processing channels Integrated digital audio processing enables the amplifier to compensate for speaker and enclosure acoustic characteristics. A programmable 7-biquad parametric equalizer for each main channel allows notching out of mechanical resonances and pre-compensation of the speaker frequency response, while programmable dynamic range compression protects from overdriving speakers and increases the average output power without increasing apparent distortion. Tone control enables 18 dB of treble and bass boost/cut, while output volume is digitally controlled in 0.5 dB steps from -100 to +28 dB via the I2C-Compliant 2-Wire interface or an analog potentiometer connected to the integrated ADC. Two independent tone generators enable mixing of multi-tone alarms and alerts into the audio channels. The auxiliary audio processing channel (Aux Channel) with optional sub-mixing and low pass filtering generates mono line level analog audio output for driving an external active subwoofer or center speaker. The main channel L/R outputs may also be connected to the PWM DAC for driving a headphone amplifier. A low jitter PLL generates internal system clocks referenced in master mode to an external crystal, or alternatively, in slave mode to either the I2S data clock (DCLK) or the audio master clock (MCLK). A buffered clock (CLKO) can be output by the device to synchronously drive companion audio devices, additional amplifiers, and switching regulators.
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4.1. PWM Processing
The Si270x is designed to operate using a bridge-tied-load (BTL) output configuration where both sides of the speaker are actively driven by the amplifier. 4.1.1. PWM Switching Rate Control The output PWM switching frequency can be programmed via 2-wire control to be half rate (480 kHz) or full rate (960 kHz). The different rates can be configured by setting property PWM_FREQ. Full Rate PWM provides better audio performance and AM radio co-existence, while Half Rate PWM provides lower switching losses and lower switching energy harmonics at high frequencies. For each configuration, the switching frequency can be offset slightly for FM band frequency planning flexibility. 4.1.2. EMI Mitigation By nature, the switching characteristic of Class D amplifiers that provides high power efficiency also creates harmonic spurs at multiples of the PWM switching rate that can radiate as EMI. Common mode PWM switching from ground to the supply translates into a radiated pattern with large energy components at the fundamental and odd harmonics of the switching frequency. Fast pulse edge transitions and differential mode ripple currents flowing through inductor windings further contribute to radiated interference. To simplify design for EMI compliance and radio receiver co-existence, the Si270x features EMI mitigation modes for managing the PWM switching noise, including pulse edge slew rate control, common mode switching noise spectral shifting, and common mode switching noise spectral spreading/shaping. 4.1.2.1. Slew Rate Control Output pulse edge slew rate can be programmed via 2-Wire control for 10 ns or 20 ns (property PWM_OUTPUT_SLEW_RATE). While faster transition times are favorable for higher efficiency, slower transition times are favorable for EMI attenuation. 4.1.2.2. Spectral Shifting The frequency locations for the PWM common mode switching energy can be shifted to facilitate frequency planning. This spectral shifting is useful for example in radios to avoid radiating interference at frequencies where the radio is being tuned. When spectral shifting is programmed for Integer Mode PWM, the common mode switching energy and harmonics are located at FC x (2n-1) for all positive integers n, where Fc is the PWM switching frequency. Alternatively, when programmed for Fractional Mode PWM, the common mode switching energy and harmonics are shifted down in frequency by 50%, and are located at FC x (2n-1)/2. The spectral shifting mode can be programmed dynamically by setting property PWM_CONFIG during normal operation without adversely affecting the internal audio processing or the amplified audio signal integrity.
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Figure 11. PWM CM Spectrum for Integer Mode PWM
Figure 12. PWM CM Spectrum for Fractional Mode PWM
4.1.2.3. Spectral Spreading Spread mode PWM can be used to spread PWM common mode switching energy resulting in a peak energy suppression greater than 20 dB at all frequencies. This Spectral Shaping feature is useful for mitigating EMI radiation and eliminating inductors for filter-less applications. Spread Mode PWM can be programmed dynamically by setting property PWM_CONFIG during normal operation without adversely affecting the internal audio processing or the differential output signal integrity. 4.1.2.4. Spectral Shaping Noise-Free Notch for AM Radio (Si2705/07 only) When using Spread Mode PWM with full rate PWM switching (960 kHz), a tunable noise-free notch can be programmed via 2-Wire control to shape the switching noise and create a narrow frequency band in the AM radio spectrum in which the PWM common mode switching energy is not allowed to spread. This noise-free notch is
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nominally 20 kHz wide and tunable in 5 kHz increments from 520 to 1710 kHz, virtually equalizing the noise level across the band. The noise-free notch can be dynamically tuned during normal operation without adversely affecting the internal audio processing or the differential output signal integrity. Spread Mode PWM with the tunable noise-free notch is useful for systems in which the Si2705/07 needs to co-exist with an AM radio receiver. In normal AM radio operation, the system MCU programs the noise-free notch frequency in the Si2705/07 to the same frequency as the AM radio to inhibit PWM switching noise from interfering with radio reception. Because Spread Mode PWM is also engaged, switching noise outside of the noise-free notch band is also suppressed for mitigating broadband EMI radiation The noise-free notch can be placed at different frequencies by programming property PWM_AM_TUNE_FREQ. More information on the complete range of programming parameters and settings available for optimized operation can be found in the "AN469: Si270x Programming Guide".
Figure 13. PWM CM Spectrum for Spread Mode PWM with Noise-Free Notch
4.2. Operating Modes
The Si2704/05/06/07 features four operating modes: one active mode (Active) and three low power modes (Standby, Sleep and Power Down). The low power modes differ on power consumption and wake up times, providing the flexibility to meet system design requirements. See Table 3, "DC Characteristics--Supplies and Interfaces," on page 6 for additional information on startup times and power consumption. Figure 14 illustrates the device state diagram highlighting the key operating modes and the allowed transitions. For more information concerning operating modes and their programming requirements, refer to "AN469: Si270x Programming Guide". 4.2.1. Active Mode Active mode is the normal operational mode in which the chip accepts digital I2S data at the input, drives an audio output and is programmable via a 2-Wire interface bus. Active Mode is initiated by setting the ACTIVE argument of the ACTIVATE command via the 2-Wire interface. To avoid clicks and pops in the audio output, mute is de-asserted after entering Active Mode.
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RESET
Assert RESET
Release RESET
Power Down Mode
POWER_DOWN POWER_UP POWER_DOWN
POWER_DOWN
Standby Mode
ACTIVATE
[ SLEEP / STANDBY ]
ACTIVATE
[ ACTIVE / STANDBY / AAD ]
Sleep Mode
ACTIVATE
[ SLEEP / ACTIVE ]
Active Mode
Figure 14. Operating Modes
4.2.2. Standby Mode Standby Mode is a reduced power state where the register states are preserved and the 2-Wire interface is fully operational, allowing for new parameters and configuration settings to be programmed even though the amplifier output is powered down. This state has the shortest wake-up time relative to the other low power modes. If the buffered reference clock output (CLKO) is enabled, the timing generation circuitry remains active. Standby Mode is initiated by setting the STANDBY argument of the ACTIVATE command via the 2-Wire interface. Standby Mode can also be initiated by setting the AAD argument of the ACTIVATE command, which additionally enables the Audio Activity Detector. See "4.5.2. Audio Activity Detector" on page 24 for additional information about this setting. To avoid clicks and pops in the audio output, mute is first asserted before entering Standby Mode. 4.2.3. Sleep Mode Sleep Mode is the lowest power consumption state in which the chip parameters and configurations are retained. However, chip parameter and configuration settings cannot be programmed and the buffered reference clock output (CLKO) is disabled in this mode. The time to activate the chip is shorter from the Sleep Mode than when activating from the Power Down Mode. Sleep mode is initiated by setting the SLEEP argument of the ACTIVATE command. 4.2.4. Power Down Mode and Reset Asserting the RST pin low disables the analog and digital circuitry, resets the registers to their default settings, and disables the 2-Wire bus. The RST pin should always be asserted low when power to the device is ramped up, and released once the power supply voltages have stabilized. After RST is released high, the chip comes up in Power Down Mode with the registers set to their default values. The 2-Wire interface remains active but only responds to the POWER_UP command that puts the device into
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Standby Mode so that the high power outputs are prevented from being enabled prior to the registers being configured. Any other command sent to the device is acknowledged on the bus but ignored by the device. This mode has the highest wake-up time and lowest power consumption of the three low power modes. A POWER_DOWN command causes a transition to Power Down Mode, disabling the outputs and resetting all parameter registers to default values.
4.3. Chip Configuration
The Si270x can be programmed via the 2-Wire interface for several operating configurations. 4.3.1. Multi-Function Pins (MFPs) Three multi-function pins (MFPs) support a wide range of system configurations while minimizing pin count. These MFPs are programmed via the 2-Wire interface. Table 13 outlines all available signals, and Table 14 shows the signal configuration options available on each MFP with the default in bold.
Table 13. Multi-Function Signal Definitions
Signal Name OUTSEL INT DIN2 DIN3 DOUT GPO1-3 Functional Description Tri-level output mode select Interrupt flag I S data input 2 I2S data input 3 I2S data output General purpose output
2
The MFPs default to High-Z state. MFP1 can be programmed to be signal INT or GPO1. MFP2 can be programmed to be signal OUTSEL, DIN2, DOUT2 or GPO2. MFP3 can be programmed to be signal DIN3, DOUT or GPO3. Table 14 summarizes the MFP configuration options with the default functionality shown in bold.
Table 14. MFP Configuration Options
Pin Name MFP1 MFP2 MFP3 Pin Number #10 (QFN) #13 (eTQFP) #11 (QFN) #14 (eTQFP) #7 (QFN) #10 (eTQFP) Signal Options High-Z, INT, GPO1 High-Z, OUTSEL, DIN2, DOUT, GPO2 High-Z, DIN3, DOUT, GPO3
The Si270x can receive digital I2S audio signal from up to three different sources with the default configuration being only one input. For cases where more than one signal input is desired or alternatively a signal output is desired, the MFPs should be programmed to an appropriate configuration with additional DINx/DOUT signals. Three general purpose output (GPO) pins are also available. The GPOs can be programmed to output logic 1, logic 0, or a Hi-Z state. These pins can be used for example to control multiplexer switches in the application via the 2-Wire bus. MFP pin function is established using the MFP_PIN_CFG command. Refer to the "AN469: Si270x Programming Guide" for more information on the options and settings requested for operation of the multi function pins.
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4.3.2. Output Mode Configuration (Si2705/07 only) The Si2705/07 can be programmed via 2-Wire or configured using the OUTSEL MFP to operate in three different output modes: 2.1 mode, 2.0 mode and aux out mode, with the 2.0 mode being the default. If OUTSEL is not configured as OUTSEL, these output modes can instead be programmed by setting the argument OUTSEL_MODE of the ACTIVATE command. Refer to the "AN469: Si270x Programming Guide" for more information on the options and settings requested for the different operation modes. OUTSEL is a three-level input with decoding to configure the analog audio signal output at AUXOL/R pins as shown in Table 15.
Table 15. OUTSEL MFP Decoding
Description OUTSEL Output Configuration Aux Out Mode 2.0 Mode 2.1 Mode H-Bridge Amplifier Aux Channel Analog Output (mono aux out) disable disable enable Main Channel Analog Output (stereo aux out) enable disable disable
GND VIO/2 VIO
disable enable enable
For stereo implementations, the 2.0 mode is selected enabling the main channel stereo power stage outputs. This is the default mode when OUTSEL is not externally driven, or when OUTSEL is driven to mid-level between VIO and GND. In 2.1 mode, with OUTSEL driven high to VIO, the main channel stereo power stage is enabled to drive stereo bridge-tied loads while a PWM DAC produces mono analog audio from the auxiliary channel to drive a subwoofer or central channel analog input amplifier. To drive an external stereo analog amplifier (e.g., for headphones) the PWM DAC can be configured to output the main stereo channel. In this case, OUTSEL is driven low to GND. To avoid unwanted audible pop noises on the output, the Si270x implements circuitry to minimize the output transients that occur while charging and discharging the PWM DAC ac coupling capacitor (see C10 and C11 in the typical application schematic on page 13). The click and pop noise reduction circuit controls the charging and discharging currents on the capacitors to prevent sudden changes in the output bias level and the consequent glitches in the output voltage.
Left channel PW M Aux channel PW M R ight channel PW M
O U TSEL
1
MUX
Left
2
2
MUX
R ight
1
Stereo PW M D AC
AU XO L
AU XO R
Figure 15. MUX OUTSEL Configuration
OUTSEL can be driven by a headphone plug detection circuit as shown in Figure 16. The ratio between the two resistors in the diagram configures the outputs for a 2.0 (with R1=R2) or a 2.1 application (with R2>>R1). In this application example, OUTSEL may be used for enabling and disabling the external amplifiers.
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R1 Audio Left OUTSEL Audio Right R2
Figure 16. Headphone Plug Detection Application Schematic
4.4. Clocking
A low jitter on-chip PLL synchronizes to an external clock reference and generates all necessary internal clocks. Three options are available for the external reference: a crystal, a reference clock or the digital I2S audio bit clock. In addition, a buffered user-programmable output clock can be generated on the CLKO pin for use as a clock reference for external circuits. 4.4.1. Reference Clock Input Using an external crystal, the on-chip crystal oscillator generates a precise, low jitter internal clock reference for the best audio performance. For system design flexibility, the device also supports the options to use either an external reference clock or the I2S bit clock as the PLL reference. Noise performance of the amplifier is a direct function of the jitter characteristics of the external source. The source of the external reference is programmed using the CLOCK_SOURCE property through the 2-Wire interface. 4.4.1.1. Crystal Oscillator Operation When a crystal is connected between XTLI and XTLO pins and the chip is configured properly all the timing for the chip is derived from the on-chip crystal oscillator. A range of crystals are supported and the device needs to be programmed to the selected frequency using the CLOCK_REF_FREQ property. The crystal oscillator provides the best audio performance. 4.4.1.2. External Reference Clock Operation In this mode, the device operates in slave clock mode and the reference clock is provided by an external clock source on pin XTLI. A wide range of input clock frequencies are supported in this mode ranging from 2.048 to 49 MHz. Refer to Table 11 on page 12 or to the "AN469: Si270x Programming Guide" for more information on the complete range of frequencies and settings required for operation on this mode. 4.4.1.3. I2S Reference Clock Operation The device can operate in slave clock mode using the DCLK signal from the I2S bus as a timing reference. In this mode the device needs to be programmed for one of the supported I2S clock rates and pin XTLI should be connected to ground. 4.4.2. Reference Clock Output The Si2704/05/06/07 may provide a buffered output clock to be used as reference for external circuits when the chip is programmed for either Active or Standby mode. The clock output frequency and synchronization source is programmable. The Si270x supports a number of reference clock frequencies that are related to the PWM switching rate. These CLKO output frequencies can be especially useful for synchronizing the amplifier to switching power supplies. Refer to the "AN469: Si270x Programming Guide" for more information on the settings requested for operation.
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4.5. Digital Audio I2S Interface
The Si270x receives digital audio data using its I2S interface. I2S inputs DIN2 and DIN3 can be configured as either an input or output while DIN is restricted to input only, and all three can be configured to operate in either master or slave mode. Only one output is supported at a time. All data ports operate synchronously from a single bit-clock and frame-clock signal. During normal operation, the crossbar mixer outputs are independently programmed to be a linear combination of any of the channels from the configured inputs with a scaling range from -1 to +1 for each channel with 8-bit precision. 4.5.1. Auto-Rate Detection The Si270x features an auto-rate detector. It actively monitors the I2S bit and frame clock inputs during operation, detects rate changes, and makes the necessary adjustments to various clock system parameters to ensure correct operation of the amplifier. 4.5.2. Audio Activity Detector The device has an audio activity detector (AAD) that monitors the presence of audio at the input. In normal operation, if the input audio level falls below a programmable threshold for a programmable period of time, it causes the device to enter the low power Standby Mode. When the input audio level subsequently increases above the threshold, the device returns to normal Active Mode. 4.5.3. Digital Audio Output The Si270x provides a bypass mode that routes I2S audio input directly to the I2S output port. The output port in turn can be connected to an off-chip device such as a DAC, DSP or digital media controller. 4.5.4. Audio data formats The digital audio interface supports 3 different audio data formats: I2S, Left-Justified and DSP Mode. In I2S mode, the MSB is captured on the second rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is low, and the right channel is transferred when the DFS is high. Figure 17 shows a diagram for the I2S digital audio format. In Left-Justified mode, the MSB is captured on the first rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB. The left channel is transferred first when the DFS is high, and the right channel is transferred when the DFS is low. Figure 18 shows a diagram for the Left-Justified digital audio format. In DSP mode, the DFS becomes a pulse, one DCLK period wide. The left channel is transferred first, followed immediately by the right channel. There are two options in transferring the digital audio data in DSP mode: the MSB of the left channel can be transferred on the first rising edge of DCLK following the DFS pulse or on the second rising edge. Figure 19 shows a diagram for the DSP digital audio format. In all audio formats, depending on the word size, DCLK frequency and sample rates, there may be unused DCLK cycles after the LSB of each word before the next DFS transition and MSB of the next word. In this event, for power saving, in I2S slave mode DCLK sent to the Si270x can be programmed to remain low until the next DFS transition appears. The device supports both rising edge and falling edge DCLK. The number of audio bits in each audio sample defaults to 24 bits and can be configured to 16, 20, 24 or 32 bits. The leading edge and the data format are selected using the DIGITAL_AUDIO_CONFIG property. 4.5.5. I2S Master Mode In master mode, the Si270x is configured for 32-bit word per audio sample, rising edge DCLK, and I2S mode data format.
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(IFALL = 1) INVERTED DCLK
(IFALL = 0)
DCLK
DFS I2S 0x00 DIN 1 DCLK n MSB n-1 n-2
LEFT CHANNEL 1 DCLK 2 1 0 LSB n MSB n-1 n-2
RIGHT CHANNEL
2
1
0 LSB
Figure 17. I2S Digital Audio Format
(IFALL = 1) INVERTED DCLK
(IFALL = 0)
DCLK
DFS Left-Justified 0x03 DOUT n MSB n-1 n-2
LEFT CHANNEL
RIGHT CHANNEL
2
1
0 LSB
n MSB
n-1
n-2
2
1
0 LSB
Figure 18. Left-Justified Digital Audio Format
(IFALL = 0) DCLK
DFS
LEFT CHANNEL DSP 0x06 DOUT (MSB at 1st rising edge) 1 DCLK DSP 0x04 DOUT (MSB at 2 rising edge)
nd
RIGHT CHANNEL 2 1 0 LSB n MSB RIGHT CHANNEL 2 1 0 LSB n MSB n-1 n-2 2 1 0 LSB n-1 n-2 2 1 0 LSB
n MSB
n-1
n-2
LEFT CHANNEL n MSB n-1 n-2
Figure 19. DSP Digital Audio Format
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4.6. Digital Audio Processing (DAP)
The Si270x implements programmable digital audio processing which features volume control, dynamic range compressor (DRC), and audio filtering such as tone control, parametric equalization, crossover, and de-emphasis. The three channel digital audio processing chain for the Si2707 is shown in Figure 20.
I2S Input 1 I2S Input 2 I2S Input 3
Crossbar Mixer
32.0 44.1kHz 48.0 L R L+R 2
Asynchronous Sample Rate Converter
48.0 kHz L1 L2 R1 R2
Tone1 Tone2
M 1 M 2
7 Bi-Quad Parametric EQ Treble/Bass Shelving Filters De-Emphasis HP Cross Over Filter Volume Master Volume Balance
2 Bi-Quad EQ
LP X-over
Volume Aux
Dynamic Range Compression DC Notch Filter Limiter
Left channel
Right channel
Aux channel
Figure 20. Signal Processing Chain
As outlined in "4.5. Digital Audio I2S Interface " on page 24, the crossbar mixer combines the selected audio sources and outputs the corresponding Left and Right main channels and an Aux Channel containing any linear combination of the inputs. The Aux Channel can either be disabled completely, configured as a mono low pass subwoofer channel, or as a mono full bandwidth center channel according to system requirement. To make all downstream audio processing independent of the input I2S clock frequencies, an asynchronous sample rate converter (ASRC) normalizes the input rate to 48 kHz. Refer to the "AN469: Si270x Programming Guide" for more information on the complete range of programming parameters and settings requested for operation of the digital audio processing features.
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4.6.1. Parametric Equalization (Si2706/07 only) The Si2706/07 includes 16 fully programmable parametric equalizer filters. Seven of these filters are implemented in each of the Left/Right main channels and the remaining two are used for the Aux Channel. The filters are implemented using a biquad form and can be programmed to shape the frequency response of each channel independently. The filters implement the configuration presented on Figure 21 which can be represented by the following equation: y[n]=b0x[n]+b1x[n-1]+b2x[n-2]+a1y[n-1]+a2y[n-2]; Where x[n] is the input sample and y[n] is the output sample.
0
-1
1
1
-1
-1
2
2
-1
Figure 21. Biquad Filter Configuration
The five coefficients for each biquad are programmed via the 2-Wire interface by using the command SET_EQ_BIQUAD_FILTER_COEFF. 4.6.2. Tone Control The Si270x implements tone control in the form of two second order shelving filters for bass and treble. Each filter has programmable cut-off frequency and boost/cut gain. Cut-off frequency can be adjusted from 5 to 20 kHz by setting properties BASS_CORNER_FREQ (for bass) and TREBLE_CORNER_FREQ (for treble). Gain can be adjusted from -18 to +18 dB in 1 dB steps by setting properties BASS_BOOST_CUT (for bass) and TREBLE_BOOST_CUT (for treble). Figure 22 shows the characteristics of the bass and treble shelving filters.
Gain
BASS Shelving Filter
Gain
TREBLE Shelving Filter
Boost
Boost
1
1
Cut Cutoff Freq Frequency Cutoff Freq
Cut
Frequency
Figure 22. Generic Bass/Treble Shelving Filter Characteristics
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4.6.3. De-Emphasis (Si2706/07 only) The Si2706/07 features a de-emphasis filtering option in order to be able to process recorded audio that for noise reasons has been subject to 50/15 s pre-emphasis. The 50/15 s filter implemented has corner frequencies at 3.183 kHz and 10.610 kHz. 4.6.4. Crossover Filter (Si2706/07 only) The Si2706/07 features a programmable frequency 12 dB/octave Linkwitz-Riley type crossover filter that provides separation of the low and high frequency content of the audio signal. The filter high-pass output is used to drive the Left/Right main channel and the low-pass output feeds the Aux Channel to be used in 2.1 Mode with an external subwoofer power driver. The cutoff frequency can be programmed from 80 to 320 Hz in 40 Hz steps via the 2-Wire interface by setting the CROSSOVER_FREQ property. The same property can also be used to disable and bypass the crossover filter. 4.6.5. Digital Volume Controls The volume control maintains a master volume for all the channels, including the Left/Right main channels and the Aux Channel. The channel volume can be set in 0.5 dB gain/attenuation steps ranging from -100 dB (mute level) to +28 dB using the VOLUME_MASTER property. To prevent audible artifacts due to volume transitions, the slope of the change in volume can be programmed by configuring the VOLUME_RAMP property. The default configuration is 0.1 dB/ms (dB per millisecond) and programming can be done in 0.1 dB/ms steps and ranging from 0.1 to 6.3 dB/ms. The device also provides balance control between the Left and Right channels through the use of the VOLUME_BALANCE property. This property specifies the audio gain/attenuation division in terms of percent split between the two channels. The Aux Channel volume control specifies the percentage of gain/attenuation levels relative to the master volume using the VOLUME_AUX_CHANNEL property. Mute is implemented using the VOLUME_MUTE. Un-muting returns the volume setting to the value stored in the volume registers at the programmed volume transition slope rate. During the mute condition, the PWM outputs switch at a 50% duty cycle.
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4.6.6. Dynamic Range Compression (Si2706/07 only) The Si2706/07 features dynamic range compression (DRC) with programmable linear gain, compression threshold, compression ratio, look ahead time, attack rate, and release rate. DRC increases the net output power without clipping by decreasing the peak amplitudes of audio signals and increasing the rms content of the lower amplitude audio signal. Audio signals below the threshold are increased by the linear gain and audio signals above the threshold are compressed by a pre-defined compression ratio. Figure 23 shows a plot of dynamic range compression audio processing with the DRC_THRESHOLD parameter set at -40 dBFS, DRC_GAIN parameter at +20 dB relative to an uncompressed transfer function and DRC_SLOPE set for a 2:1 compression ratio. For input signals below the compression threshold of -40 dBFS, the output signal is increased by 20 dB relative to the input signal. For input signals above the compression threshold the input signal is increased by 1 dB for every 2 dB increase in audio input level.
Figure 23. Dynamic Range Compression Example
In this example, the input dynamic range of 90 dB is reduced to an output dynamic range of 70 dB. Figure 24 shows the time domain response of the dynamic range compression. The DRC_ATTACK_TIME parameter sets how quickly the gain compression responds to changes in the input level, and the DRC_RELEASE_TIME parameter sets how quickly the gain compression returns to linear gain once the audio input level drops below the compression threshold. DRC_LOOKAHEAD_TIME allows setting the look ahead time that permits the DRC circuit to adjust the compression to sudden level changes thus preventing the clipping of the fast changing signal. Refer to "AN503: Si270x Class-D Amplifier--Dynamic Range Compressor Use" for additional information.
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Figure 24. Time Domain Characteristics of the Audio Dynamic Range Controller
4.6.7. Hard Signal Limiter The device implements a hard limiter to avoid exceeding the maximum modulation rate of the amplifier. The hard limiter is always enabled. 4.6.8. DC Notch Filter A dc notch filter with a 5 Hz corner frequency is implemented as the final function in the signal processing chain to remove any dc component from the output signal. Each channel has a separate dc notch filter. 4.6.9. Tone and Alert Generation The Si270x includes two independent tone generators with programmable frequencies and on/off times. The output of both tone generators is fed to a mixer which combines the tones with the I2S inputs. The tones' amplitudes can be adjusted by programming the mixer coefficients using the SET_AUDIO_INPUT_MIXER command. This feature allows customization of audible alarms and alerts. Programmable frequencies range from 100 Hz to 20 kHz in 100 Hz steps and on/off times range from 0 to 65 seconds in 1 ms steps and are set via the 2-Wire interface using the properties TONE_ONE_FREQ, TONE_ONE_ON_TIME, TONE_ONE_OFF_TIME, and TONE_ONE_AMPLITUDE for the first tone and TONE_TWO_FREQ, TONE_TWO_ON_TIME, TONE_TWO_OFF_TIME, and TONE_TWO_AMPLITUDE for the second tone.
4.7. Fault Detection and Response
To help protect the H-bridge driver and external loads, the output stage has fault detection circuitry that allows the device to respond to over-current and over-temperature events. The over-temperature circuitry monitors the temperature of the device and if the temperature exceeds 135 C a thermal error is issued, and the output stage is shut down by transitioning the device to Standby Mode. The over-current protection circuit constantly monitors the current of the output stage and triggers a fault alarm if an over-current condition is detected from three different events: a short circuit across the speaker terminals, a short circuit of any of the outputs to ground and a short circuit of any of the outputs to the supply voltage. In each case, the detector issues a fault if the 2.5 A current threshold is exceeded. In response to this fault the device power stage is shut down by transitioning the device to Standby Mode.
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4.8. Power Supply and Grounding Considerations
Careful attention should be given to the power and ground routing to allow for optimal performance of the Si270x. The low voltage supplies, VDD and VIO, should be decoupled with 0.1 F capacitors soldered as close to the device as possible so that parasitic inductances are minimized. For the power stage supplies VPPL and VPPR, each should be bypassed with a 0.1 F in ceramic capacitor, located as close to the device as possible, in parallel with a 220 F electrolytic capacitor. This allows for optimal filtering in the full frequency spectrum. For detailed information on board layout considerations and examples refer to "AN470: Si270x Layout Guidelines."
4.9. Control Interface
An I2C-compatible 2-Wire serial port slave interface allows an external controller to send commands, configure properties, and receive responses from the Si270x. Commands may only be sent after VIO and VDD supplies are applied and the RST pin has been released high. The CLKO pin serves as a configuration boot-strap to select one of two unique addresses to which the Si270x responds. During reset, if CLKO is pulled low using a 2.2 k resistor connected to ground, then the 7 bit device address is 1001010 (0x94). If CLKO is left floating, a 22 k internal pull-up within the Si270x causes the 2-Wire to select a device address of 0011011 (0x36). A 2-wire transaction begins with the START condition, which occurs when SDIO falls while SCLK is high. Next, the 2-wire master drives an 8-bit control word serially on SDIO which is captured by the device on rising edges of SCLK. The control word consists of a 7 bit device address followed by a read/write bit (read = 1, write = 0). If the address matches, the Si270x acknowledges the control word by driving SDIO low on the next falling edge of SCLK. For write operations, the 2-Wire master sends an eight bit data byte on SDIO following the control word, which is captured by the device on rising edges of SCLK. The Si270x acknowledges each data byte by driving SDIO low for one cycle, on the next falling edge of SCLK. The 2-Wire master may write up to eight data bytes during a single 2-wire transaction. The first byte is a command, and the next seven bytes are arguments. For read operations, after the Si270x has acknowledged the control byte, it drives a data byte on SDIO, changing the state of SDIO on the falling edge of SCLK. The 2-wire master acknowledges each data byte by driving SDIO low for one cycle on the next falling edge of SCLK. If a data byte is not acknowledged, the transaction ends. The 2-wire master may read up to 16 data bytes in a single 2-wire transaction. These bytes contain the response data from the Si270x. A 2-wire transaction ends with the STOP condition, which occurs when SDIO rises while SCLK is high. For details on timing specifications and diagrams, refer to Table 8 on page 9, Figure 3 on page 11, and Figure 4 on page 11.
4.10. Programming with Commands
The Si270x provides a simple yet powerful software interface to program configuration and parameter settings. The device is programmed using commands, arguments, properties, and responses. To perform an action, the user writes a command byte and associated arguments causing the chip to execute the given command. Commands control actions, such as powering up the device, shutting down the device, or configure the audio input source. Arguments are specific to a given command and are used to modify the command. For example, for the SET_AUDIO_INPUT_MIXER command, arguments are required to set the coefficients of the linear combination of the sources. Properties are a special command argument used to modify the default chip operation and are generally configured immediately after power up. Examples of properties include CLOCK_SOURCE and DEEMPHASIS. A complete list of commands and properties is available in "5. Commands and Properties". Responses provide the user information and are returned after a command and associated arguments are sent. At a minimum, all commands respond with a one-byte status reply indicating interrupt and clear-to-send status information. Subsequent sections of this data sheet mention many of the commands and properties that are used to alter different functions. More information on the complete list of programming modes of operation and properties can be found in the "AN469: Si270x Programming Guide."
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5. Commands and Properties
Table 16 and Table 17 are the summary of commands and properties for the Si270x Class D Audio Amplifier device.
Table 16. Class D Audio Amplifier Command Summary
Common Commands Number 0x01 0x10 0x12 0x13 0x14 0x15 0x16 0x21 0x22 0x23 0x24 0x31 0x32 POWER_UP FUNC_INFO SET_PROPERTY GET_PROPERTY MFP_PIN_CFG SET_AUDIO_INPUT_MIXER OUTSEL SET_EQ_BIQUAD_FILTER_COEFF GET_INT_STATUS GET_FAULT_STATUS GET_AUDIO_STATUS ACTIVATE POWER_DOWN Name Power-up the device. Returns the Function revision information of the device. Set the value of a property. Retrieve a property's value. Configure MFP pins. Configure Audio input source. Select amplifier outputs. Set Biquad Filter. Read interrupt status bit. Get the source of the fault condition. Read back audio parameters. Enable or disable audio processing & amplifier output operations. Power-down the device. Summary
Table 17. Class D Audio Amplifier Property Summary
Category Number Interrupt Clock 0x0001 0x0101 0x0102 0x0103 I2S AAD 0x0104 0x0201 0x0301 0x0302 INT_ENABLE REF_CLOCK_SOURCE REF_CLOCK_FREQ CLOCK_OUT_FREQ DIGITAL_AUDIO_SAMPLE_RATE DIGITAL_AUDIO_CONFIG AAD_CONFIG AAD_THRESHOLD Name Summary Configure Interrupt Source. Select the reference source for PLL. Set the reference clock freq for the PLL in kHz units. Configure output clock frequency. Set the digital audio sampling rate. Sets the Digital Audio Input Format Configuration. Set Audio Activity Detector (AAD) Configuration. Set audio level threshold where the device will go into standby if the audio input level falls below this threshold. Set how long the signal has been below the threshold in ms before going to standby state.
0x0303
AAD_DURATION
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Table 17. Class D Audio Amplifier Property Summary (Continued)
Category Number Biquad Filter 0x1901 0x2103 0x2104 0x2105 0x2106 Volume 0x2201 0x2202 0x2203 0x2204 0x2205 DRC 0x2301 0x2302 0x2303 0x2304 0x2305 0x2306 0x2307 PWM 0x2701 0x2702 0x2703 0x2704 0x2705 Programmable Tone 0x2901 0x2902 0x2903 0x2904 0x2905 0x2906 0x2907 0x2908 Name CROSSOVER_FREQ BASS_BOOST_CUT BASS_CORNER_FREQ TREBLE_BOOST_CUT TREBLE_CORNER_FREQ VOLUME_MUTE VOLUME_MASTER VOLUME_BALANCE VOLUME_AUX_CHANNEL VOLUME_RAMP DRC_CONFIG DRC_THRESHOLD DRC_SLOPE DRC_GAIN DRC_ATTACK_TIME DRC_RELEASE_TIME DRC_LOOKAHEAD_SAMPLES PWM_CONFIG PWM_FREQ PWM_AM_TUNE_FREQ Summary Set crossover freq between Main Channel and Aux Channel. Set bass shelving filter boost/cut for the Left and Right Channel. Set bass shelving filter corner freq for the Left and Right Channel. Set treble shelving filter boost/cut for the Left and Right Channel. Set treble shelving filter corner freq for the Left and Right Channel. Mute speaker output. Set Master Volume. Set L and R Volume Balance from 0% to 100%. Set Aux Channel Volume. Set volume transition slope. Configure DRC. Set DRC threshold. Set the DRC slope. DRC slope is the inverse of DRC compression ratio. Set DRC gain. Set DRC attack time constant in ms units. Set DRC release time constant in ms units. Sets the number of look-ahead samples. Set PWM Output Mode and Max Modulation Index. Set PWM Freq in kHz units. Set where the currently AM Tune Freq is to put the notch when EMI mitigation mode is used. Set output stage slew rate. Set programmable tone generator amplitude. Set programmable tone generator frequency. Set programmable tone generator ON Time in ms. Set programmable tone generator OFF Time in ms. Set programmable tone generator amplitude. Set programmable tone generator frequency. Set programmable tone generator ON Time in ms. Set programmable tone generator OFF Time in ms.
PWM_MAX_MODULATION_INDEX Set PWM maximum modulation index. PWM_OUTPUT_SLEW_RATE TONE_ONE_AMPLITUDE TONE_ONE_FREQ TONE_ONE_ON_TIME TONE_ONE_OFF_TIME TONE_TWO_AMPLITUDE TONE_TWO_FREQ TONE_TWO_ON_TIME TONE_TWO_OFF_TIME
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6. Pin Descriptions
6.1. 24-Pin QFN Package
XTLO VPPL 19 18 17 GND PAD (Back Paddle) 16 15 14 Top Down View 24-Pin QFN Package 7 MFP3 8 AUXOL 9 AUXOR 10 MFP1 11 OUTSEL/MFP2 12 VPPR 13 OUTPL OUTNL GNDL GNDR OUTNR OUTPR VDD XTLI RST 20 DFS 24 DCLK DIN VIO SCLK SDIO CLKO 1 2 3 4 5 6
23
22
21
Figure 25. Pin Configuration Table 18. Pin Descriptions
Pin Number GND PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name GND DCLK DIN VIO SCLK SDIO CLKO MFP3 AUXOL AUXOR MFP1 OUTSEL/MFP2 VPPR OUTPR OUTNR GNDR GNDL OUTNL OUTPL VPPL RST XTLO XTLI VDD DFS I2S digital I/O data clock. I2S digital data input port. I/O supply voltage. Serial clock input for I2C-compliant 2-Wire control interface. Serial data input/output for I2C-compliant 2-Wire control interface. Buffered reference clock output. Configures 2-Wire address on RST. Multi-function pin 3. PWMDAC left channel analog output on Si2705/07 (Reserved on Si2704/06). PWMDAC right channel analog output on Si2705/07 (Reserved on Si2704/06). Multi-function pin 1. Output select three-level control input: 2.0, 2.1 or line out mode. Right channel power stage supply voltage. Right channel power stage "P" output. Right channel power stage "N" output. Right channel power stage ground. Left channel power stage ground. Left channel power stage "N" output. Left channel power stage "P" output. Left channel power stage supply voltage. Device reset (active low) input. External crystal output. Reference clock or external crystal input. Low voltage supply voltage. I2S digital I/O data frame synch. Function Low voltage ground for VDD. Connect to PCB ground plane.
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6.2. 48-Pin eTQFP Package
RSTB XTLO GND VDD XTLI NC NC NC NC NC NC
38
48
47
46
45
44
43
42
41
40
39
37 36 35 34 33 32 31
NC DFS DCLK DIN VIO GND SCLK SDIO CLKO NC NC NC
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NC VPPL OUTPL GND OUTNL GNDL GNDR OUTNR GND OUTPR VPPR NC
GND PAD (Back Paddle)
30 29 28 27 26
Top Down View 48-Pin eTQFP Package
16 17 18 19 20 21 22 23 24
25
GND
NC
VOL/MFP1
OUTSEL/MFP2
NC
NC
SLEEP/MFP3
AUXOL
AUXOR
NC
NC
Figure 26. Pin Configuration Table 19. Pin Descriptions
Pin Number 1, 10, 11, 12, 13, 14, 15, 16, 23, 24, 25, 36, 37, 38, 39, 45, 46, 47, 48 2 3 4 5 6, 20, 28, 33, 43 7 8 9 17 18 19 21 22 26 27 Name NC Function No connect. Connect to PCB ground plane.
DFS DCLK DIN VIO GND SCLK SDIO CLKO MFP3 AUXOL AUXOR MFP1 OUTSEL/MFP2 VPPR OUTPR
I2S digital I/O data frame synch. I2S digital I/O data clock. I2S digital data input port. I/O supply voltage. Ground. Connect to PCB ground plane. Serial clock input for I2C-compliant 2-Wire control interface. Serial data input/output for I2C-compliant 2-Wire control interface. Buffered reference clock output. Configures 2-Wire address on RST. Multi-function pin 3. PWMDAC left channel analog output on Si2705/07 (Reserved on Si2704/06). PWMDAC right channel analog output on Si2705/07 (Reserved on Si2704/06). Multi-function pin 1. Output select three-level control input: 2.0, 2.1 or line out mode. Right channel power stage supply voltage. Right channel power stage "P" output.
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Table 19. Pin Descriptions (Continued)
Pin Number 29 30 31 32 34 35 40 41 42 44 Name OUTNR GNDR GNDL OUTNL OUTPL VPPL RST XTLO XTLI VDD Function Right channel power stage "N" output. Right channel power stage ground. Left channel power stage ground. Left channel power stage "N" output. Left channel power stage "P" output. Left channel power stage supply voltage. Device reset (active low) input. External crystal output. Reference clock or external crystal input. Low voltage supply voltage.
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7. Ordering Guide
Part Number* SI2704-A10-GM SI2704-A10-GQ Si2705-A10-GM Si2705-A10-GQ Si2706-A10-GM Si2706-A10-GQ Si2707-A10-GM Si2707-A10-GQ Description 2.0 EMI Mitigating Class D Power Amplifier 2.0 EMI Mitigating Class D Power Amplifier 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio 2.0 EMI Mitigating Class D Power Amplifier with EQ/DRC 2.0 EMI Mitigating Class D Power Amplifier with EQ/DRC 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio with EQ/DRC 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio with EQ/DRC Package Type 4x4 QFN Pb-Free 7x7 eTQFP Pb-Free 4x4 QFN Pb-Free 7x7 eTQFP Pb-Free 4x4 QFN Pb-Free 7x7 eTQFP Pb-Free 4x4 QFN Pb-Free 7x7 eTQFP Pb-Free Operating Temperature -20 to 85 C -20 to 85 C -20 to 85 C -20 to 85 C -20 to 85 C -20 to 85 C -20 to 85 C -20 to 85 C
*Note: Add an "R" at the end of the device part number to denote tape and reel option.
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8. Package Outline
8.1. 24-Pin QFN Package
Figure 27 illustrates the package details for 24-pin QFN package option for the Si2704/05/06/07. Table 20 lists the values for the dimensions shown in the illustration.
Figure 27. 24-Pin QFN Table 20. 24-Pin QFN Package Dimensions
Dimension A A1 b D D2 e E 2.40 Min 0.80 0.00 0.18 Nom 0.85 0.02 0.25 4.00 BSC 2.50 0.50 BSC 4.00 BSC 2.60 Max 0.90 0.05 0.30 Dimension E2 L aaa bbb ccc ddd eee Min 2.40 0.20 -- -- -- -- -- Nom 2.50 0.25 -- -- -- -- -- Max 2.60 0.30 0.10 0.10 0.08 0.10 0.10
Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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8.2. 48-Pin eTQFP Package
Figure 28 illustrates the package details for 48-pin eTQFP package option for the Si2704/05/06/07. Table 21 lists the values for the dimensions shown in the illustration.
Figure 28. 48-Pin eTQFP
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Table 21. 48-Pin eTQFP Package Dimensions
Dimension A A1 A2 b c D D1 D2 e 3.71 Min -- 0.05 0.95 0.17 0.09 Nom -- -- 1.00 0.22 -- 9.00 BSC 7.00 BSC 3.81 0.50 BSC 3.91 Max 1.20 0.15 1.05 0.27 0.20 Dimension E E1 E2 L aaa bbb ccc ddd 3.71 0.45 -- -- -- -- 0 Min Nom 9.00 BSC 7.00 BSC 3.81 0.60 -- -- -- -- 3.5 3.91 0.75 0.20 0.20 0.08 0.08 7 Max
Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. 3. This drawing conforms to JEDEC outline MS-026, variation ABC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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9. Package Markings (Top Marks)
9.1. Si2707 Top Mark (QFN)
9.2. Top Mark Explanation
Mark Method Line 1 Marking YAG Laser Part Number 04 = Si2704 05 = Si2705 06 = Si2706 07 = Si2707 10 = Firmware Revision 1.0 A = Revision A Die Internal Tracking Code Pin 1 Identifier Assigned by the Assembly House. Corresponds to the year and work week of the mold date.
Firmware Revision Line 2 Marking Line 3 Marking Die Revision TTTTT = Internal Code Circle = 0.5 mm Diameter (Bottom-Left Justified) YY = Year WW = Work Week
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9.3. Si2707 Top Mark (eTQFP)
9.4. Top Mark Explanation
Mark Method Line 1 Marking YAG Laser Part Number Si2704 Si2705 Si2706 Si2707 10 = Firmware Revision 1.0 A = Revision A Die Internal Tracking Code Pin 1 Identifier Assigned by the Assembly House. Corresponds to the year and work week of the mold date.
Firmware Revision Line 2 Marking Line 3 Marking Die Revision TTTTT = Internal Code Circle = 0.5 mm Diameter (Bottom-Left Justified) YY = Year WW = Work Week
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10. Additional Reference Resources

Si270x Evaluation Board User's Guide AN469: 270x Programming Guide AN470: 270x Layout Guidelines AN502: Si270x Class-D Amplifier--Analog Source Setup AN503: Si270x Class-D Amplifier--Dynamic Range Compressor Use AN504: Si270x Class-D Amplifier--Dynamic Bass Configuration AN505: Si270x Class-D Amplifier--Measuring Output Power AN509: Si270x Class-D Amplifier--Ferrite Bead Filter AN510: Si270x Class-D Amplifier--Calculating Filter Loss Si270x Customer Support Site: http://www.silabs.com This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA is required for access to some of these documents. To request access, send mysilabs user name and request for access to AudioInfo@silabs.com.
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DOCUMENT CHANGE LIST
Revision 0.4 to Revision 0.5

Updated Table 3 on page 6. Updated Table 4 on page 7. Updated Table 5 on page 7. Updated Table 6 on page 8. Updated Table 11 on page 12. Updated "2. Typical Application Schematic" on page 13. Updated Figure 15 on page 22.
Added "4.5.5. I2S Master Mode" on page 24. Added note to "7. Ordering Guide" on page 37. Added "9. Package Markings (Top Marks)" on page 41. Added "9.3. Si2707 Top Mark (eTQFP)" on page 42.
Revision 0.5 to Revision 0.6

Updated eTQFP pin assignments on pages 1 and 35. Updated eTQFP pin descriptions in Table 19 on page 35. Updated Table 1 on page 5. Updated Table 3 on page 6. Updated Table 4 on page 7. Updated Table 5 on page 7. Updated Table 11 on page 12. Updated "2. Typical Application Schematic" on page 13. Updated "3. Typical System Configurations" on page 14
Updated Updated
Figure 6 on page 14. Figure 9 on page 15.
Updated "4. Functional Description" on page 16. Updated "4.4.1.2. External Reference Clock Operation" on page 23. Updated "5. Commands and Properties" on page 32.
Updated Updated
Table 16 on page 32. Table 17 on page 32.
Updated "10. Additional Reference Resources" on page 43.
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NOTES:
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CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Audioinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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